1. Field of the Invention
The present invention relates to systems for and methods of testing of multiple semiconductor devices on testing boards. More specifically, it relates to more efficient methods and systems of testing semiconductor devices. Most especially, it relates to such systems and methods in which the semiconductor devices are tested in parallel and in which round trip delays in signal paths for input test signals and resulting output signals from the devices are substantially eliminated.
2. Description of the Prior Art
When fabrication of integrated circuits and other semiconductor devices, such as dynamic random access memory (DRAM) or flash memory devices, has been completed, the semiconductor devices are subjected to burn-in and electrical tests in order to identify and eliminate defective semiconductor devices before shipment to a customer. The term "burn-in" relates to operation of an integrated circuit at a predetermined temperature or temperature profile, typically an elevated temperature in an oven. Certain operating electrical bias levels and/or signals are supplied to the semiconductor devices while they are at the elevated temperature. The use of the elevated temperature accelerates stress to which the devices are subjected during burn-in, so that marginal devices that would otherwise fail shortly after being placed in service fail during burn-in and are eliminated before shipping. In electrical test, a more complete set of operating electrical bias levels and signals are supplied to the device to provide a thorough evaluation of its functions.
Commonly assigned U.S. Pat. No. 5,682,472, issued Oct. 27, 1997 to Jeffrey A. Brehm and Patrick M. Shepherd, the disclosure of which is hereby incorporated by reference herein, discloses a prior art example of a burn in method and system, which is configured to test large numbers of semiconductor devices in parallel. In one aspect of that system, different round trip delay compensation time is provided for different ones of the semiconductor devices under test (DUTs), based on different signal path lengths to the devices.
The use of such variable round trip delay compensation results in a significant performance enhancement of such a system for testing large numbers of semiconductor devices in parallel. In particular, the Assignee's commercially available MTX parallel test and burn-in system is able to operate at a test signal rate of 20 MHz as a result of using the variable round trip delay compensation. This compares to a typical burn-in test signal rate of 5 MHz for burn-in systems prior to the MTX parallel test and burn-in system.
As integrated circuit operating speeds increase, there is a corresponding increase in speed requirements for burn-in systems and methods. For example, among the highest performance memory integrated circuits are those that comply with the Rambus standard. Those memory integrated circuits operate at a signal rate of up to 800 MHz. While a parallel test and burn-in system like the MTX system cannot measure AC performance of such high frequency Rambus integrated circuits, the circuits can be operated at much lower speeds for functional testing with an MTX or similar burn-in and test system. Clearly, if the AC performance of such a highly parallel test and burn-in system can be improved, allowing higher frequency integrated circuits to be operated at higher frequencies than possible with the current MTX parallel test and burn-in system for functional testing, a higher throughput and consequently lower cost per integrated circuit functional testing is permitted. Therefore, the present invention is directed to improving such a parallel test and burn-in system to allow test signal rates of 30 MHz and higher to be achieved.
In addition to parallel test and burn-in systems for functional testing, much higher performance single head testers are known in the art and are employed for AC testing of integrated circuits. Such single head testers often incorporate a variety of features to make them operable at higher frequencies.
Such single head testers are described, for example, in M. Mydill, "A Test System Architecture to Reduce Transmission Line Effects During High Speed Testing," IEEE International Test Conference, Paper 29.3, pp. 701-709 and J. A. Gasbarro et al., "Techniques for Characterizing DRAMS with a 500 MHz Interface," IEEE International Test Conference, Paper 22.2, pp. 516-525. These papers disclose a technique for substantially eliminating round trip delay in such single head testers, but the direct application of this technique in a parallel test and burn-in system is problematical, because, as disclosed, it requires the use of two tester channels per DUT I/O pin, which reduces the efficiency of a parallel test and burn-in system by 50 percent. Further development is therefore required to allow substantial elimination of round trip delay in a parallel test and burn-in system without paying a substantial efficiency penalty in such a system.
Such a typical prior art VLSI (Very Large Scale Integration) semiconductor device single head testing system is shown in FIG. 1. VLSI refers to the placement of a large number (over 1000) of device elements, such as transistors, on integrated circuits. The Device Under Test 10 (DUT) is connected to a driver channel 12 for inputting driver signals into the DUT and a receiver channel 14 for receiving signals from the DUT that will be tested. Round Trip Delay (RTD) is a measure of the total amount of time required for a signal to propagate from one end of a trace line (the tester in FIG. 1) to the other end and back to its point of origin (the tester). In FIG. 1, RTD would be equivalent to the time required for a signal to travel from the test drive 12 to the DUT 10 and back to the receiver channel of the tester 14. Notably, neither of these channels can both drive and receive signals in this implementation. Also, this method has not been used in burn-in systems which usually have I/Os from multiple DUTs tied to one tester channel.
An existing method used to test DUTs on burn-in boards is shown in FIG. 2. A tester 20 connects to DUTs 21 to be tested at two interfaces/pins, such as 22 and 24. The tester input driver 25 connects to the DUT inputs as shown at 22, and the tester I/O driver 26 connects to the DUT I/O drivers as shown at 24. The input driver 25 produces a test signal periodically that results in correct data at the output of DUTs operating. The physical trace line length between tester drives 25 and 26 and rows of DUTs 21 may be 2-3 feet, and the propagation delay (Pd) for these traces typically ranges from 7 to 12 nanoseconds. The propagation delay resulting from the sum of the input and output lengths is referred to as Round Trip Delay (RTD) and is an important limitation on testing cycle speed in testing systems such as that shown in FIG. 2.
Tester input driver 25 typically will have more DUTs connected to it than will the tester I/O driver 26 and much better line termination. The tester I/O driver typically is connected to 8 different DUT I/O pins. All grouped DUT I/O pins receive inputs in parallel, but only one selected DUT in an I/O group is enabled at one time through multiplexing to drive the I/O line 27 for testing. The signal sent by that DUT on the I/O line 27 is inputted to a comparator 28 and a latch 29 which constitute the test logic that determines if the DUT signal sent on I/O line 27 is the proper level.
FIG. 3 shows a timing diagram illustrating how signals propagate through the testing network of FIG. 2. Each of the traces 30, 31, and 3220 represent the signal level at the points labeled A, B, and C, respectively, in FIG. 2. Each of the vertical hash marks at the left of the traces 30, 31, and 32 denote a time of zero nanoseconds. The input to the comparator at C after 50 nanoseconds should mimic the low level outputs 34, but it does not because a new driver input signal which is seen at C is sent by the driver 26 at 50 nanoseconds, contending with delayed DUT output at C at the beginning of the next test cycle. In order for the proper low-level outputs from the DUTs to be seen at the comparator input C, the 50 nanosecond tester I/O cycle 36 must be extended by 24 nanoseconds, the Round Trip Delay 38. As a result, the input signals from the test driver do not interfere with or cancel out output signals from DUTs that will serve as inputs to test circuitry. If the cycle is not extended, only a 1 nanosecond pulse output 39 will be seen at the comparator input C.
The RTD for the prior art can be a wide range for different devices. This wide range can make it difficult to make timing measurements on the devices such as the propagation delay time or the access time. An accurate RTD time is necessary to know how much system delay to subtract off the timing measurement. There is usually some compensation within the test hardware for some fixed amount of RTD.
Moreover the DUTs' I/O drivers are the weakest current drivers in the driver chain. The weak DUT I/O driver limits maximum test speed. Furthermore, proper termination for tester I/O drivers in the input state cannot be obtained because proper input termination at DUTs generally cannot be achieved. This is because DUT output drivers cannot drive proper input termination. Tester input drivers have much stronger current delivery capability than DUT output drivers. In an attempt to partially compensate for this problem, the circuit pictured in FIG. 2 has a small series resistor positioned between the DUT and tester comparator and approximately equidistant from both.
Capacitance is added on the DUT I/O output pin as more DUT I/O pins are grouped in parallel with one another, limiting tester speeds.
Long trace lines limit tester speed. Tester I/O drivers can be moved very close to DUTs, but this results in higher costs due to increased cooling requirements. It also results in lower quantities of DUTs per cubic area that can be tested in the burn-in oven.